Reference number
ISO/IEC 18372:2004
International Standard
ISO/IEC 18372:2004
Information technology — RapidIO(TM) interconnect specification
Edition 1
2004-12
Read sample
ISO/IEC 18372:2004
38668
Published (Edition 1, 2004)
This publication was last reviewed and confirmed in 2018. Therefore this version remains current.

Abstract

The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and high performance embedded applications. It is intended primarily as an intra-system interface, allowing chip-to-chip and board-toboard communications at Gigabyte per second performance levels. It provides a rich variety of features including high data bandwidth, low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, message passing, and software managed programming models.

General information

  •  : Published
     : 2004-12
    : International Standard confirmed [90.93]
  •  : 1
     : 405
  • ISO/IEC JTC 1/SC 25
    35.100.30 
  • RSS updates

Got a question?

Check out our Help and Support